1. Lumped or distributed circuit element? A uniform lossless
transmission line with the L and C parameters and the length l given as
shown in Figure is excited by a unit step source with rise-time equal to
tr = 0.1 ns. Determine the following: (a) The characteristic impedance
Z0 and the one-way time delay td of the transmission line. (b) Whether
it is appropriate or not to model the transmission line in this circuit
as a lumped element.Figure Transmission line. Problem.... Get solution
2. Lumped- or distributed-circuit element? A uniform lossless transmission line is used to connect a periodic pulse waveform to a load as shown in Figure Assuming the characteristic impedance and phase velocity of the transmission line to be, respectively, Z0 = 50Ω and vp = 2c/3, determine the following: (a) The per-unit-length parameters L and C of the transmission line. (b) The one-way propagation time delay td of the transmission line. (c) Whether this transmission line can be treated as a lumped element or not.Figure Transmission line. Problem.... Get solution
3. Open-circuited line. Consider the circuit shown in Figure, with an ideal unit step source connected to a lossless line of characteristic impedance Z0 = 50Ω having an open-circuited termination at the other end. Assuming a one-way propagation delay across the line of td , use a bounce diagram to sketch the load voltage VL(t ) versus time for 0 ≤ t ≤ 10td .Figure Open-circuited line. Problem.... Get solution
4. Step and pulse excitation of a lossless line. A uniform, lossless transmission line is excited with a step source as shown in Figure (a) Provide an appropriate bounce diagram and use it to sketch both the source-end voltage Vs and the load-end voltage VL as a function of time between 0 and 10 ns. Provide all the pertinent values on your sketches. (b) Repeat part (a) if the step voltage source was a pulse source given by 10 [u(t ) − u(t − 0.3 ns)] V.Figure Step and pulse excitation of a lossless line. Problem.... Get solution
5. Resistive loads. The circuit shown in Figure consists of an uncharged transmission line connected to a load resistance RL. Assuming that the switch closes at t = 0, sketch the load voltage VL(t ) over the time interval 0 ≤ t ≤ 3 ns for the following load resistances: (a) RL = 25Ω, (b) RL = 50Ω, (c) RL = 100Ω.Figure Resistive loads. Problems 2.5 and...Discharging of a charged line. For the circuit of Problem. assume that the switch has been closed for a long time before it opens at t = 0. Sketch the load voltage _L(t ) over 0 ≤ t ≤ 3 ns for the same three cases Get solution
6. Ringing. The transmission line system shown in Figure is excited by a step-voltage source of amplitude 3.6 V and source impedance 10Ω at one end and is terminated with an open circuit at the other end. The line is characterized by the line parameters L = 0.5 μHm −1, C = 0.2 nF-m−1, R = 0, G = 0, and has a length of l = 30 cm. Sketch the load voltage VL(t ) over 0 ≤ t ≤ 10 ns with the steady-state value indicated.Figure Ringing. Problem.... Get solution
7. Discharging of a charged line. For the circuit of Problem. assume that the switch has been closed for a long time before it opens at t = 0. Sketch the load voltage VL(t ) over 0 ≤ t ≤ 3 ns for the same three cases.Resistive loads. The circuit shown in Figure consists of an uncharged transmission line connected to a load resistance RL. Assuming that the switch closes at t = 0, sketch the load voltage VL(t ) over the time interval 0 ≤ t ≤ 3 ns for the following load resistances: (a) RL = 25Ω, (b) RL = 50Ω, (c) RL = 100Ω.Figure Resistive loads. Problems 2.5 and 2.7... Get solution
8. Two step voltage sources. Consider the lossless transmission-line circuit which is excited by two step voltage sources, as shown in Figure. Use a bounce diagram to sketch the voltages V1 and V2 as a function of time. Note that the step-voltage source on the left side turns off at t = 0.Figure Pulse excitation. Problem.... Get solution
9. Pulse excitation. The circuit shown in Figure is excited by an ideal voltage pulse of 1 V amplitude starting at t = 0. Given the length of the line to be l = 10 cm and the propagation speed to be 20 cm-(ns)−1; (a) sketch the voltage at the source end of the line, Vs(t ), for an input pulse duration of 10 ns; (b) repeat part (a) for an input pulse duration of 1 ns.Figure Pulse excitation. Problem... Get solution
10. Pulse excitation. The circuit shown in Figure is excited with a voltage pulse of amplitude A and pulse width tw. Assuming the propagation delay of the line to be td , sketch the load voltage VL(t ) versus t for 0 ≤ t ≤ 10td for (a) tw = 2td, (b) tw = td, and (c) tw = td /2.Figure Pulse excitation. Problem.... Get solution
11. Observer on the line. A transmission line with an unknown characteristic impedance Z0 terminated in an unknown load resistance RL, as shown in Figure, is excited by a pulse source of amplitude 1 V and duration tw = 3td /4, where td is the one-way flight time of the transmission line. An observer at the center of the line observes the voltage variation shown. (a) Determine Z0 and RL. (b) Using the values found in (a), sketch the voltage variation (up to t = 4td ) that would be observed by the same observer if the pulse duration were tw = 1.5td.Figure Observer on the line. Problem.... Get solution
12. Cascaded transmission lines. For the transmission line circuit shown in Figure, sketch Vs(t ) and VL(t ) over 0 ≤ t ≤ 5 ns.Figure Cascaded lines. Problem.... Get solution
13. Time-domain reflectometry (TDR). A TDR is used to test the transmission line system shown in Figure. Using the sketch of Vs(t ) observed on the TDR scope as shown, determine the values of Z01, l1, and R1. Assume the phase velocity of the waves to be 20 cm-(ns)−1 on each line. Plot VR1(t ) versus t for 0 ≤ t ≤ 4 ns.Figure Time-domain reflectometry. Problem.... Get solution
14. Time-domain reflectometry (TDR). TDR measurements can also be used in cases with more than one discontinuity. Two transmission lines of different characteristic impedances and time delays terminated by a resistive load are being tested by a TDR, as shown in Figure (a) Given the TDR display of the source-end voltage due to a 3-V, 100Ω step excitation starting at t = 0, find the characteristic impedances (Z01 and Z02) and the time delays (td1 and td2) of both lines, and the unknown load RL. (b) Using the values found in part (a), find the time and magnitude of the next change in the source-end voltage Vs(t ), and sketch it on the display.Figure Time-domain reflectometry. Problem.... Get solution
15. Time-domain reflectometry (TDR). Consider the circuit shown in Figure. The two line segments are of equal length l. Assuming the propagation speeds on the two lines are equal to 15 cm-(ns)−1 each, find Z01, Z02, RL, and l using the TDR display of the source voltage Vs(t ), as shown.Figure Time-domain reflectometry. Problem.... Get solution
16. Multiple lines. In the three lossless transmission-line circuit shown in Figure, the switch closes at t = 0. Assuming all the lines to be uncharged before t = 0, draw a bounce diagram and sketch voltages Vs, VL1, and VL2 between t = 0 and t = 10 ns using the impedance and time delay values indicated on Figure.Figure Multiple lines. Problem.... Get solution
17. Digital IC chips. Two impedance-matched, in-package-terminated Integrated Circuit (IC) chips are driven from an impedance-matched IC chip, as shown in Figure. Assuming the lengths of the interconnects to be 15 cm each and the propagation velocity on each to be 10 cm-(ns)−1, do the following: (a) Sketch the voltagesVL1 and VL2 for a time interval of 10 ns. Indicate the steady-state values on your sketch. (b) Repeat part (a) if one of the load IC chips is removed from the end of the interconnect connected to it (i.e., the load point A is left open-circuited).Figure Digital IC chips. Problem.... Get solution
18. Multiple lines. For the distributed interconnect system shown in Figure, and for Z01 = Z02 = 50Ω, find and sketch the three load voltages V1(t ), V2(t ), and V3(t ) for a time interval of 5 ns. Assume each interconnect to have a one-way time delay of 1 ns. (b) Repeat part (a) for Z01 = Z02 = 25Ω.Figure Multiple lines. Problem.... Get solution
19. Reflections due to parasitic effects. The circuit shown in Figure consists of a low-impedance driver driving a distributed interconnect system that was intended to be impedance-matched, with Z0 = 120Ω. An engineer performs some tests and measurements and observes reflections due to parasitic effects associated with the two interconnects terminated at the 120Ω loads. Assuming that the effective characteristic impedances of these interconnects (i.e., taking parasitic effects into account) is such that we have Z0 = 80Ω instead of 120Ω, find and sketch the voltages V1(t ) and V2(t ) for 0 ≤ t ≤ 12 ns, assuming the one-way time delay on each interconnect to be 2 ns. Comment on the effects of the mismatch caused by parasitic effects. Assume the initial incident wave launched at the driver end of the 60Ω line to be V+ 1 = 4 V.Figure Reflections due to mismatches. Problem.... Get solution
20. Parallel multiple lines. The transmission line system shown in Figure consists of three lines, each having Z0 = 50Ω and a one-way propagation delay of 1 ns. (a) Find and sketch the voltages Vs(t ) and VL(t ) versus t for 0 ≤ t ≤ 10 ns. (b) Repeat part (a) when the open-circuited ends are terminated with a load resistance of 50Ω each.Figure Parallel multiple lines. Problem.... Get solution
21. Optimized multiple lines. A multisection transmission line consists of three lossless transmission lines used to connect an ideal step source of 5V amplitude and 6Ω output impedance to two separate load resistances of 66Ω each, as shown in Figure All three lines are characterized by line parameters L = 364.5 nH-m−1, and C = 125 pF-m−1. To minimize ringing effects, the line lengths are optimized to be of equal length. If each line length is l = 40 cm, sketch the voltages Vs and VL versus t for 0 ≤ t ≤ 20 ns, and comment on the performance of the circuit in minimizing ringing.Figure Optimized multiple lines. Problem.... Get solution
22. Transient response of a cascaded transmission-line circuit. Consider a circuit consisting of two cascaded lossless transmission lines with characteristic impedances and one-way time delays as shown in Figure. Assuming both lines to be fully discharged before t = 0, sketch the source-end, junction and load-end voltages Vs, VJ, and VL as a function of time for the time interval 0 ≤ t ≤ 10td for the following three cases: (a) Rs = Z0 and RL = 3Z0, (b) Rs = Z0 and RL = Z0, (c) Rs = Z0/3 and RL = 3Z0.Figure Cascaded transmission line. Problem.... Get solution
23. Charging and discharging of a line. For the transmission line system shown in Figure, the switch S2 is closed at t = 2td (where td is the propagation delay of each line) after the switch S1 is closed at t = 0. Find and sketch the voltage VL versus t for 0 ≤ t ≤ 6td.Figure Charging and discharging of a line. Problem.... Get solution
24. Digital IC interconnect. A circuit consists of one logic gate driving an identical gate via a 1-ft-long, 50Ω interconnect. Before t = 0, the output of the driver gate is at LOW voltage state and can simply be approximated as a 14Ω resistor. At t = 0, the output of the driver gate goes from LOW to HIGH state and can be approximated with a 5-V voltage source in series with a 14Ω resistor. The input of the load gate can be approximated to be an open circuit (i.e., RL =∞). Assuming that a minimum load voltage of 3.75 V is required to turn and keep the load gate on, (a) find the time at which the load gate will turn on for the first time. (b) Find the time at which the load gate will turn on permanently. (Assume a signal time delay of 1.5 ns-ft−1 along the interconnect for both parts.) Get solution
25. Terminated IC interconnects. The logic circuit of Problem needs to be modified to eliminate ringing. Two possible solutions are to terminate the line in its characteristic impedance at either the source (series termination) or receiver (parallel termination) end. Both of these circuits are shown in Figure (a) Select the value of the termination resistance RT in both circuits to eliminate ringing. (b) Compare the performance of these two circuits in terms of their speed and dc power dissipation. Which technique is the natural choice for a design to achieve low-power dissipation at steady state?Figure Terminated IC interconnects. (a) Series termination. (b) Parallel termination. Problem....Digital IC interconnect. A circuit consists of one logic gate driving an identical gate via a 1-ft-long, 50Ω interconnect. Before t = 0, the output of the driver gate is at LOW voltage state and can simply be approximated as a 14Ω resistor. At t = 0, the output of the driver gate goes from LOW to HIGH state and can be approximated with a 5-V voltage source in series with a 14Ω resistor. The input of the load gate can be approximated to be an open circuit (i.e., RL =∞). Assuming that a minimum load voltage of 3.75 V is required to turn and keep the load gate on, (a) find the time at which the load gate will turn on for the first time. (b) Find the time at which the load gate will turn on permanently. (Assume a signal time delay of 1.5 ns-ft−1 along the interconnect for both parts.) Get solution
26. Digital IC gate interconnects. A disadvantage of the series termination scheme in Problem is that the receiver gate or gates must be near the end of the line to avoidreceiving a two-step signal. This scheme is not recommended for terminating distributed loads. The two circuits shown in Figure have three distributed loads equally positioned along a 3-ft-long 50Ω interconnect on a pc board constructed of FR4 material (take vp ≃ 14.3 cm-(ns)−1). Each circuit uses a different termination scheme. Assuming the driver and all the loads to be the same gates as in Problem. find the times at which each load gate changes its logic state after the output voltage of the driver gate switches to HIGH state at t = 0. Comment on the performance of both circuits and indicate which termination scheme provides faster speed. (Use some of the data provided in Problem.)Figure IC gate interconnects. (a) Series termination. (b) Parallel termination. Problem....Terminated IC interconnects. The logic circuit of Problem needs to be modified to eliminate ringing. Two possible solutions are to terminate the line in its characteristic impedance at either the source (series termination) or receiver (parallel termination) end. Both of these circuits are shown in Figure (a) Select the value of the termination resistance RT in both circuits to eliminate ringing. (b) Compare the performance of these two circuits in terms of their speed and dc power dissipation. Which technique is the natural choice for a design to achieve low-power dissipation at steady state?Figure Terminated IC interconnects. (a) Series termination. (b) Parallel termination. Problem....Digital IC interconnect. A circuit consists of one logic gate driving an identical gate via a 1-ft-long, 50Ω interconnect. Before t = 0, the output of the driver gate is at LOW voltage state and can simply be approximated as a 14Ω resistor. At t = 0, the output of the driver gate goes from LOW to HIGH state and can be approximated with a 5-V voltage source in series with a 14Ω resistor. The input of the load gate can be approximated to be an open circuit (i.e., RL =∞). Assuming that a minimum load voltage of 3.75 V is required to turn and keep the load gate on, (a) find the time at which the load gate will turn on for the first time. (b) Find the time at which the load gate will turn on permanently. (Assume a signal time delay of 1.5 ns-ft−1 along the interconnect for both parts.) Get solution
27. Digital IC circuit. For the digital IC circuit shown in Figure, the driver gate goes from LOW to HIGH state at t = 0, and its Thévenin equivalent circuit (including the series termination resistance) can be approximated as a 5-V voltage source in series with a 50Ω resistor. If the time delay for all interconnects is given to be 2 ns-ft−1, find the time at which each receiver gate changes its state permanently. Assume each load gate to change state when its input voltage exceeds 4 V. Also assume each load gate to appear as an open circuit at its input. Support your solution with sketches of the two load voltages V1 and V2 as functions of time for a reasonable time interval.Figure Digital IC circuit. Problem.... Get solution
28. Two driver gates. Two identical logic gates drive a third identical logic gate (load gate), as shown in Figure. All interconnects have the same one-way time delay td and characteristic impedance Z0. When any one of these driver gates is at HIGH state, its Thévenin equivalent as seen from its output terminals consists of a voltage source with voltage V0 in series with a resistance of value Rs = Z0. At LOW state, its Thévenin equivalent is just a resistance of value Rs = Z0. The input impedance of the load gate is very high compared with the characteristic impedance of the line (i.e., Zin ≫ Z0). (a) Assuming steady-state conditions before both driver gates change to HIGH state at t = 0, sketch the load voltage VL as a function of time for 0 ≤ t ≤ 7td . What is the eventual steady-state value of the load voltage? (b) Assume steady-state conditions before t = 0 to be such that driver gate 1 is at HIGH state and gate 2 is at LOW state. At t = 0, gate 1 and gate 2 switch states. Repeat part (a).Figure Two driver gates. Problem.... Get solution
29. Capacitive load. For the transmission line system shown in Figure, the switch is closed at t = 0. Each of the two transmission lines has a one-way time delay of 2 ns. Assuming both transmission lines and the 5 pF capacitor to be initially uncharged, find and sketch the voltage V1(t ) across the resistor R1.Figure Capacitive load. Problem.... Get solution
30. Unknown lumped element. Using the source-end voltage waveform observed on the TDR display due to an ideal step voltage source exciting the double lossless transmission line circuit connected as shown in Figure, determine the type of the unknown lumped element at the junction and its value.Figure Unknown lumped element. Problem.... Get solution
31. Unknown lumped element. The transmission line circuit has an unknown lumped element, as shown in Figure. With the source-end voltage due to step excitation measured to be as plotted, determine the type of the unknown element, and find its value in terms of the shaded area A.Figure Unknown lumped element. Problem.... Get solution
32. Source-end TDR waveform. The source-end TDR voltage waveform of a transmission-line circuit terminated with three unknown lumped elements is as shown in Figure Using this waveform, (a) determine the characteristic impedance and the one-way time delay of the line and (b) the types and the values of the three unknown elements.Figure Source-end TDR waveform. Problem.... Get solution
33. Unknown load. A 5 V dc voltage source is used to excite a lossless transmission-line circuit terminated with two unknown lumped elements, as shown in Figure. The switch at the source end is closed at t = 0. The transmission line parameters Z0, td , and length L are unknown. Based on the source-end TDR voltage waveform shown in Figure, determine the type (resistor, capacitor, or inductor) and values of the two unknown lumped elements. Assume the transmission line to be at steady-state condition at t = 0–.Figure Unknown load. Problem.... Get solution
34. Capacitive load. Two transmission lines of characteristic impedances 75Ω and 50Ω are joined by a connector that introduces a shunt resistance of 150Ω between the lines, as shown in Figure. The load end of the 50Ω line is terminated with a capacitive load with a 30 pF capacitor initially uncharged. The source end of the 75Ω line is excited by a step function of amplitude 3.6 V and a series resistance of 75Ω, starting at t = 0. Assuming the total time delay of each line to be td1 = 6 ns and td2 = 2 ns, respectively, find and sketch (a) the voltage VL(t ) at the load end of the 50Ω line and (b) the voltage Vs(t ) at the source end of the 75Ω line.Figure Capacitive load. Problem.... Get solution
35. Reactive element at the junction. In the lossless transmission-line circuit shown in Figure, find and sketch both the source-end voltage Vs and the load-end voltage VL as a function of time.Figure Reactive element at the junction. Problem.... Get solution
36. Transmission line terminated with a capacitive load. Consider the lossless transmission-line circuit shown in Figure where the switch at the load end closes at t = 0, after being open for a long time. Find and sketch the source-end and the load-end voltages Vs(t ) and VL(t ).Figure Transmission line terminated with a capacitive load. Problem.... Get solution
37. Transients on a transmission line. Consider the lossless transmission-line circuit as shown in Figure The switch is opened at t =0, after being closed for a long time. Find and sketch the source-end voltage Vs (t ) as a function of time.Figure Transients on a transmission line. Problem.... Get solution
38. Transient response. Consider the lossless transmission line system shown in Figure. The 20 pF capacitor is initially uncharged. The switch S is initially open but is closed at t =7 ns. Determine mathematical expressions for and sketch the capacitor voltage VC(t ) and the source-end voltage Vs(t ) for 0≤t ≤12 ns. Make assumptions as needed but clearly state and justify them.Figure Transients on a transmission line. Problem.... Get solution
39. Inductive load. Two transmission lines of characteristic impedances 50Ω and 75Ω are joined by a connector that introduces a series resistance of 25Ω between the lines, as shown in Figure. The load end of the 75Ω line is terminated with an inductive load. The inductor is initially uncharged, and a step source with amplitude s v turns on at t = 0. Find and sketch the voltage VL. First determine the initial and final values and accurately mark all points of your sketch.Figure Inductive load. Problem.... Get solution
40. Capacitive load. A step-type incident voltage wave of 1-V peak value arrives at a capacitive load at t = 0, as shown in Figure. After t = 0, find the approximate time at which the reflected voltage wave V– at the load position z = 0 is equal to zero. Assume the load capacitor to be initially uncharged.Figure Capacitive load. Problem.... Get solution
41. Step excitation. The circuit shown in Figure is excited by a step-voltage source of amplitude 5 V and source resistance Rs = 2Z0, starting at t = 0. Note that the characteristic impedance of the shorted stub is half that of the main line and that the second segment of the main line is twice as long, so its one-way time delay is 2td . (a) Assuming the load to be an open circuit (i.e., a very large resistance), sketch the load voltage VL(t ) versus t for 0 ≤ t ≤ 11t . (b) Repeat part (a) for the case when the input is a pulse of duration tw = 4td.Figure Step excitation. Problem.... Get solution
42. Capacitive load excited by two sources. For the transmission line system shown in Figure, find the mathematical expression for the capacitor voltage Vc (t ) and sketch it for t ≥ 0. Assume the capacitor to be initially uncharged.Figure Capacitive load excited by two sources. Problem.... Get solution
43. Two sources. For the circuit shown in Figure, sketch the voltages Vs1(t ) and Vs2(t ) for 0 ≤ t ≤ 7td .Figure Two sources. Problem.... Get solution
44. RG 8 coaxial line. A student buys an RG 8 low-loss coaxial cable for a VHF antenna project. He looks up the specifications of the RG 8 coax in a product catalog and finds out that its characteristic impedance is Z0 = 50 Ω, its velocity factor is vp/c = 0.66, and its line capacitance is C = 26.4 pF-ft−1. He then cuts a portion of this coax and measures the diameter of the inner conductor and the outer diameter of the dielectric to be approximately 2 mm and 7.5 mm, respectively. Using these values, find or verify the values of the unit length line parameters L, C, R, and G and the characteristic impedance Z0 of this cable at 100 MHz. Note that the dielectric inside RG 8 coax is polyethylene and that the leakage conductance per unit length of a polyethylene-filled coaxial line at 100 MHz is approximately given by G ≃ 1.58 × 10−5/ ln(b/a) S-m−1. Get solution
45. Two-wire line. Calculate the per-unit-length line parameters L, C, R, and G and the characteristic impedance Z0 of an air-insulated two-wire line made of copper wires with wire separation of 2.1 cm and wire diameter of 1.2 mm at a frequency of 200 MHz. Get solution
2. Lumped- or distributed-circuit element? A uniform lossless transmission line is used to connect a periodic pulse waveform to a load as shown in Figure Assuming the characteristic impedance and phase velocity of the transmission line to be, respectively, Z0 = 50Ω and vp = 2c/3, determine the following: (a) The per-unit-length parameters L and C of the transmission line. (b) The one-way propagation time delay td of the transmission line. (c) Whether this transmission line can be treated as a lumped element or not.Figure Transmission line. Problem.... Get solution
3. Open-circuited line. Consider the circuit shown in Figure, with an ideal unit step source connected to a lossless line of characteristic impedance Z0 = 50Ω having an open-circuited termination at the other end. Assuming a one-way propagation delay across the line of td , use a bounce diagram to sketch the load voltage VL(t ) versus time for 0 ≤ t ≤ 10td .Figure Open-circuited line. Problem.... Get solution
4. Step and pulse excitation of a lossless line. A uniform, lossless transmission line is excited with a step source as shown in Figure (a) Provide an appropriate bounce diagram and use it to sketch both the source-end voltage Vs and the load-end voltage VL as a function of time between 0 and 10 ns. Provide all the pertinent values on your sketches. (b) Repeat part (a) if the step voltage source was a pulse source given by 10 [u(t ) − u(t − 0.3 ns)] V.Figure Step and pulse excitation of a lossless line. Problem.... Get solution
5. Resistive loads. The circuit shown in Figure consists of an uncharged transmission line connected to a load resistance RL. Assuming that the switch closes at t = 0, sketch the load voltage VL(t ) over the time interval 0 ≤ t ≤ 3 ns for the following load resistances: (a) RL = 25Ω, (b) RL = 50Ω, (c) RL = 100Ω.Figure Resistive loads. Problems 2.5 and...Discharging of a charged line. For the circuit of Problem. assume that the switch has been closed for a long time before it opens at t = 0. Sketch the load voltage _L(t ) over 0 ≤ t ≤ 3 ns for the same three cases Get solution
6. Ringing. The transmission line system shown in Figure is excited by a step-voltage source of amplitude 3.6 V and source impedance 10Ω at one end and is terminated with an open circuit at the other end. The line is characterized by the line parameters L = 0.5 μHm −1, C = 0.2 nF-m−1, R = 0, G = 0, and has a length of l = 30 cm. Sketch the load voltage VL(t ) over 0 ≤ t ≤ 10 ns with the steady-state value indicated.Figure Ringing. Problem.... Get solution
7. Discharging of a charged line. For the circuit of Problem. assume that the switch has been closed for a long time before it opens at t = 0. Sketch the load voltage VL(t ) over 0 ≤ t ≤ 3 ns for the same three cases.Resistive loads. The circuit shown in Figure consists of an uncharged transmission line connected to a load resistance RL. Assuming that the switch closes at t = 0, sketch the load voltage VL(t ) over the time interval 0 ≤ t ≤ 3 ns for the following load resistances: (a) RL = 25Ω, (b) RL = 50Ω, (c) RL = 100Ω.Figure Resistive loads. Problems 2.5 and 2.7... Get solution
8. Two step voltage sources. Consider the lossless transmission-line circuit which is excited by two step voltage sources, as shown in Figure. Use a bounce diagram to sketch the voltages V1 and V2 as a function of time. Note that the step-voltage source on the left side turns off at t = 0.Figure Pulse excitation. Problem.... Get solution
9. Pulse excitation. The circuit shown in Figure is excited by an ideal voltage pulse of 1 V amplitude starting at t = 0. Given the length of the line to be l = 10 cm and the propagation speed to be 20 cm-(ns)−1; (a) sketch the voltage at the source end of the line, Vs(t ), for an input pulse duration of 10 ns; (b) repeat part (a) for an input pulse duration of 1 ns.Figure Pulse excitation. Problem... Get solution
10. Pulse excitation. The circuit shown in Figure is excited with a voltage pulse of amplitude A and pulse width tw. Assuming the propagation delay of the line to be td , sketch the load voltage VL(t ) versus t for 0 ≤ t ≤ 10td for (a) tw = 2td, (b) tw = td, and (c) tw = td /2.Figure Pulse excitation. Problem.... Get solution
11. Observer on the line. A transmission line with an unknown characteristic impedance Z0 terminated in an unknown load resistance RL, as shown in Figure, is excited by a pulse source of amplitude 1 V and duration tw = 3td /4, where td is the one-way flight time of the transmission line. An observer at the center of the line observes the voltage variation shown. (a) Determine Z0 and RL. (b) Using the values found in (a), sketch the voltage variation (up to t = 4td ) that would be observed by the same observer if the pulse duration were tw = 1.5td.Figure Observer on the line. Problem.... Get solution
12. Cascaded transmission lines. For the transmission line circuit shown in Figure, sketch Vs(t ) and VL(t ) over 0 ≤ t ≤ 5 ns.Figure Cascaded lines. Problem.... Get solution
13. Time-domain reflectometry (TDR). A TDR is used to test the transmission line system shown in Figure. Using the sketch of Vs(t ) observed on the TDR scope as shown, determine the values of Z01, l1, and R1. Assume the phase velocity of the waves to be 20 cm-(ns)−1 on each line. Plot VR1(t ) versus t for 0 ≤ t ≤ 4 ns.Figure Time-domain reflectometry. Problem.... Get solution
14. Time-domain reflectometry (TDR). TDR measurements can also be used in cases with more than one discontinuity. Two transmission lines of different characteristic impedances and time delays terminated by a resistive load are being tested by a TDR, as shown in Figure (a) Given the TDR display of the source-end voltage due to a 3-V, 100Ω step excitation starting at t = 0, find the characteristic impedances (Z01 and Z02) and the time delays (td1 and td2) of both lines, and the unknown load RL. (b) Using the values found in part (a), find the time and magnitude of the next change in the source-end voltage Vs(t ), and sketch it on the display.Figure Time-domain reflectometry. Problem.... Get solution
15. Time-domain reflectometry (TDR). Consider the circuit shown in Figure. The two line segments are of equal length l. Assuming the propagation speeds on the two lines are equal to 15 cm-(ns)−1 each, find Z01, Z02, RL, and l using the TDR display of the source voltage Vs(t ), as shown.Figure Time-domain reflectometry. Problem.... Get solution
16. Multiple lines. In the three lossless transmission-line circuit shown in Figure, the switch closes at t = 0. Assuming all the lines to be uncharged before t = 0, draw a bounce diagram and sketch voltages Vs, VL1, and VL2 between t = 0 and t = 10 ns using the impedance and time delay values indicated on Figure.Figure Multiple lines. Problem.... Get solution
17. Digital IC chips. Two impedance-matched, in-package-terminated Integrated Circuit (IC) chips are driven from an impedance-matched IC chip, as shown in Figure. Assuming the lengths of the interconnects to be 15 cm each and the propagation velocity on each to be 10 cm-(ns)−1, do the following: (a) Sketch the voltagesVL1 and VL2 for a time interval of 10 ns. Indicate the steady-state values on your sketch. (b) Repeat part (a) if one of the load IC chips is removed from the end of the interconnect connected to it (i.e., the load point A is left open-circuited).Figure Digital IC chips. Problem.... Get solution
18. Multiple lines. For the distributed interconnect system shown in Figure, and for Z01 = Z02 = 50Ω, find and sketch the three load voltages V1(t ), V2(t ), and V3(t ) for a time interval of 5 ns. Assume each interconnect to have a one-way time delay of 1 ns. (b) Repeat part (a) for Z01 = Z02 = 25Ω.Figure Multiple lines. Problem.... Get solution
19. Reflections due to parasitic effects. The circuit shown in Figure consists of a low-impedance driver driving a distributed interconnect system that was intended to be impedance-matched, with Z0 = 120Ω. An engineer performs some tests and measurements and observes reflections due to parasitic effects associated with the two interconnects terminated at the 120Ω loads. Assuming that the effective characteristic impedances of these interconnects (i.e., taking parasitic effects into account) is such that we have Z0 = 80Ω instead of 120Ω, find and sketch the voltages V1(t ) and V2(t ) for 0 ≤ t ≤ 12 ns, assuming the one-way time delay on each interconnect to be 2 ns. Comment on the effects of the mismatch caused by parasitic effects. Assume the initial incident wave launched at the driver end of the 60Ω line to be V+ 1 = 4 V.Figure Reflections due to mismatches. Problem.... Get solution
20. Parallel multiple lines. The transmission line system shown in Figure consists of three lines, each having Z0 = 50Ω and a one-way propagation delay of 1 ns. (a) Find and sketch the voltages Vs(t ) and VL(t ) versus t for 0 ≤ t ≤ 10 ns. (b) Repeat part (a) when the open-circuited ends are terminated with a load resistance of 50Ω each.Figure Parallel multiple lines. Problem.... Get solution
21. Optimized multiple lines. A multisection transmission line consists of three lossless transmission lines used to connect an ideal step source of 5V amplitude and 6Ω output impedance to two separate load resistances of 66Ω each, as shown in Figure All three lines are characterized by line parameters L = 364.5 nH-m−1, and C = 125 pF-m−1. To minimize ringing effects, the line lengths are optimized to be of equal length. If each line length is l = 40 cm, sketch the voltages Vs and VL versus t for 0 ≤ t ≤ 20 ns, and comment on the performance of the circuit in minimizing ringing.Figure Optimized multiple lines. Problem.... Get solution
22. Transient response of a cascaded transmission-line circuit. Consider a circuit consisting of two cascaded lossless transmission lines with characteristic impedances and one-way time delays as shown in Figure. Assuming both lines to be fully discharged before t = 0, sketch the source-end, junction and load-end voltages Vs, VJ, and VL as a function of time for the time interval 0 ≤ t ≤ 10td for the following three cases: (a) Rs = Z0 and RL = 3Z0, (b) Rs = Z0 and RL = Z0, (c) Rs = Z0/3 and RL = 3Z0.Figure Cascaded transmission line. Problem.... Get solution
23. Charging and discharging of a line. For the transmission line system shown in Figure, the switch S2 is closed at t = 2td (where td is the propagation delay of each line) after the switch S1 is closed at t = 0. Find and sketch the voltage VL versus t for 0 ≤ t ≤ 6td.Figure Charging and discharging of a line. Problem.... Get solution
24. Digital IC interconnect. A circuit consists of one logic gate driving an identical gate via a 1-ft-long, 50Ω interconnect. Before t = 0, the output of the driver gate is at LOW voltage state and can simply be approximated as a 14Ω resistor. At t = 0, the output of the driver gate goes from LOW to HIGH state and can be approximated with a 5-V voltage source in series with a 14Ω resistor. The input of the load gate can be approximated to be an open circuit (i.e., RL =∞). Assuming that a minimum load voltage of 3.75 V is required to turn and keep the load gate on, (a) find the time at which the load gate will turn on for the first time. (b) Find the time at which the load gate will turn on permanently. (Assume a signal time delay of 1.5 ns-ft−1 along the interconnect for both parts.) Get solution
25. Terminated IC interconnects. The logic circuit of Problem needs to be modified to eliminate ringing. Two possible solutions are to terminate the line in its characteristic impedance at either the source (series termination) or receiver (parallel termination) end. Both of these circuits are shown in Figure (a) Select the value of the termination resistance RT in both circuits to eliminate ringing. (b) Compare the performance of these two circuits in terms of their speed and dc power dissipation. Which technique is the natural choice for a design to achieve low-power dissipation at steady state?Figure Terminated IC interconnects. (a) Series termination. (b) Parallel termination. Problem....Digital IC interconnect. A circuit consists of one logic gate driving an identical gate via a 1-ft-long, 50Ω interconnect. Before t = 0, the output of the driver gate is at LOW voltage state and can simply be approximated as a 14Ω resistor. At t = 0, the output of the driver gate goes from LOW to HIGH state and can be approximated with a 5-V voltage source in series with a 14Ω resistor. The input of the load gate can be approximated to be an open circuit (i.e., RL =∞). Assuming that a minimum load voltage of 3.75 V is required to turn and keep the load gate on, (a) find the time at which the load gate will turn on for the first time. (b) Find the time at which the load gate will turn on permanently. (Assume a signal time delay of 1.5 ns-ft−1 along the interconnect for both parts.) Get solution
26. Digital IC gate interconnects. A disadvantage of the series termination scheme in Problem is that the receiver gate or gates must be near the end of the line to avoidreceiving a two-step signal. This scheme is not recommended for terminating distributed loads. The two circuits shown in Figure have three distributed loads equally positioned along a 3-ft-long 50Ω interconnect on a pc board constructed of FR4 material (take vp ≃ 14.3 cm-(ns)−1). Each circuit uses a different termination scheme. Assuming the driver and all the loads to be the same gates as in Problem. find the times at which each load gate changes its logic state after the output voltage of the driver gate switches to HIGH state at t = 0. Comment on the performance of both circuits and indicate which termination scheme provides faster speed. (Use some of the data provided in Problem.)Figure IC gate interconnects. (a) Series termination. (b) Parallel termination. Problem....Terminated IC interconnects. The logic circuit of Problem needs to be modified to eliminate ringing. Two possible solutions are to terminate the line in its characteristic impedance at either the source (series termination) or receiver (parallel termination) end. Both of these circuits are shown in Figure (a) Select the value of the termination resistance RT in both circuits to eliminate ringing. (b) Compare the performance of these two circuits in terms of their speed and dc power dissipation. Which technique is the natural choice for a design to achieve low-power dissipation at steady state?Figure Terminated IC interconnects. (a) Series termination. (b) Parallel termination. Problem....Digital IC interconnect. A circuit consists of one logic gate driving an identical gate via a 1-ft-long, 50Ω interconnect. Before t = 0, the output of the driver gate is at LOW voltage state and can simply be approximated as a 14Ω resistor. At t = 0, the output of the driver gate goes from LOW to HIGH state and can be approximated with a 5-V voltage source in series with a 14Ω resistor. The input of the load gate can be approximated to be an open circuit (i.e., RL =∞). Assuming that a minimum load voltage of 3.75 V is required to turn and keep the load gate on, (a) find the time at which the load gate will turn on for the first time. (b) Find the time at which the load gate will turn on permanently. (Assume a signal time delay of 1.5 ns-ft−1 along the interconnect for both parts.) Get solution
27. Digital IC circuit. For the digital IC circuit shown in Figure, the driver gate goes from LOW to HIGH state at t = 0, and its Thévenin equivalent circuit (including the series termination resistance) can be approximated as a 5-V voltage source in series with a 50Ω resistor. If the time delay for all interconnects is given to be 2 ns-ft−1, find the time at which each receiver gate changes its state permanently. Assume each load gate to change state when its input voltage exceeds 4 V. Also assume each load gate to appear as an open circuit at its input. Support your solution with sketches of the two load voltages V1 and V2 as functions of time for a reasonable time interval.Figure Digital IC circuit. Problem.... Get solution
28. Two driver gates. Two identical logic gates drive a third identical logic gate (load gate), as shown in Figure. All interconnects have the same one-way time delay td and characteristic impedance Z0. When any one of these driver gates is at HIGH state, its Thévenin equivalent as seen from its output terminals consists of a voltage source with voltage V0 in series with a resistance of value Rs = Z0. At LOW state, its Thévenin equivalent is just a resistance of value Rs = Z0. The input impedance of the load gate is very high compared with the characteristic impedance of the line (i.e., Zin ≫ Z0). (a) Assuming steady-state conditions before both driver gates change to HIGH state at t = 0, sketch the load voltage VL as a function of time for 0 ≤ t ≤ 7td . What is the eventual steady-state value of the load voltage? (b) Assume steady-state conditions before t = 0 to be such that driver gate 1 is at HIGH state and gate 2 is at LOW state. At t = 0, gate 1 and gate 2 switch states. Repeat part (a).Figure Two driver gates. Problem.... Get solution
29. Capacitive load. For the transmission line system shown in Figure, the switch is closed at t = 0. Each of the two transmission lines has a one-way time delay of 2 ns. Assuming both transmission lines and the 5 pF capacitor to be initially uncharged, find and sketch the voltage V1(t ) across the resistor R1.Figure Capacitive load. Problem.... Get solution
30. Unknown lumped element. Using the source-end voltage waveform observed on the TDR display due to an ideal step voltage source exciting the double lossless transmission line circuit connected as shown in Figure, determine the type of the unknown lumped element at the junction and its value.Figure Unknown lumped element. Problem.... Get solution
31. Unknown lumped element. The transmission line circuit has an unknown lumped element, as shown in Figure. With the source-end voltage due to step excitation measured to be as plotted, determine the type of the unknown element, and find its value in terms of the shaded area A.Figure Unknown lumped element. Problem.... Get solution
32. Source-end TDR waveform. The source-end TDR voltage waveform of a transmission-line circuit terminated with three unknown lumped elements is as shown in Figure Using this waveform, (a) determine the characteristic impedance and the one-way time delay of the line and (b) the types and the values of the three unknown elements.Figure Source-end TDR waveform. Problem.... Get solution
33. Unknown load. A 5 V dc voltage source is used to excite a lossless transmission-line circuit terminated with two unknown lumped elements, as shown in Figure. The switch at the source end is closed at t = 0. The transmission line parameters Z0, td , and length L are unknown. Based on the source-end TDR voltage waveform shown in Figure, determine the type (resistor, capacitor, or inductor) and values of the two unknown lumped elements. Assume the transmission line to be at steady-state condition at t = 0–.Figure Unknown load. Problem.... Get solution
34. Capacitive load. Two transmission lines of characteristic impedances 75Ω and 50Ω are joined by a connector that introduces a shunt resistance of 150Ω between the lines, as shown in Figure. The load end of the 50Ω line is terminated with a capacitive load with a 30 pF capacitor initially uncharged. The source end of the 75Ω line is excited by a step function of amplitude 3.6 V and a series resistance of 75Ω, starting at t = 0. Assuming the total time delay of each line to be td1 = 6 ns and td2 = 2 ns, respectively, find and sketch (a) the voltage VL(t ) at the load end of the 50Ω line and (b) the voltage Vs(t ) at the source end of the 75Ω line.Figure Capacitive load. Problem.... Get solution
35. Reactive element at the junction. In the lossless transmission-line circuit shown in Figure, find and sketch both the source-end voltage Vs and the load-end voltage VL as a function of time.Figure Reactive element at the junction. Problem.... Get solution
36. Transmission line terminated with a capacitive load. Consider the lossless transmission-line circuit shown in Figure where the switch at the load end closes at t = 0, after being open for a long time. Find and sketch the source-end and the load-end voltages Vs(t ) and VL(t ).Figure Transmission line terminated with a capacitive load. Problem.... Get solution
37. Transients on a transmission line. Consider the lossless transmission-line circuit as shown in Figure The switch is opened at t =0, after being closed for a long time. Find and sketch the source-end voltage Vs (t ) as a function of time.Figure Transients on a transmission line. Problem.... Get solution
38. Transient response. Consider the lossless transmission line system shown in Figure. The 20 pF capacitor is initially uncharged. The switch S is initially open but is closed at t =7 ns. Determine mathematical expressions for and sketch the capacitor voltage VC(t ) and the source-end voltage Vs(t ) for 0≤t ≤12 ns. Make assumptions as needed but clearly state and justify them.Figure Transients on a transmission line. Problem.... Get solution
39. Inductive load. Two transmission lines of characteristic impedances 50Ω and 75Ω are joined by a connector that introduces a series resistance of 25Ω between the lines, as shown in Figure. The load end of the 75Ω line is terminated with an inductive load. The inductor is initially uncharged, and a step source with amplitude s v turns on at t = 0. Find and sketch the voltage VL. First determine the initial and final values and accurately mark all points of your sketch.Figure Inductive load. Problem.... Get solution
40. Capacitive load. A step-type incident voltage wave of 1-V peak value arrives at a capacitive load at t = 0, as shown in Figure. After t = 0, find the approximate time at which the reflected voltage wave V– at the load position z = 0 is equal to zero. Assume the load capacitor to be initially uncharged.Figure Capacitive load. Problem.... Get solution
41. Step excitation. The circuit shown in Figure is excited by a step-voltage source of amplitude 5 V and source resistance Rs = 2Z0, starting at t = 0. Note that the characteristic impedance of the shorted stub is half that of the main line and that the second segment of the main line is twice as long, so its one-way time delay is 2td . (a) Assuming the load to be an open circuit (i.e., a very large resistance), sketch the load voltage VL(t ) versus t for 0 ≤ t ≤ 11t . (b) Repeat part (a) for the case when the input is a pulse of duration tw = 4td.Figure Step excitation. Problem.... Get solution
42. Capacitive load excited by two sources. For the transmission line system shown in Figure, find the mathematical expression for the capacitor voltage Vc (t ) and sketch it for t ≥ 0. Assume the capacitor to be initially uncharged.Figure Capacitive load excited by two sources. Problem.... Get solution
43. Two sources. For the circuit shown in Figure, sketch the voltages Vs1(t ) and Vs2(t ) for 0 ≤ t ≤ 7td .Figure Two sources. Problem.... Get solution
44. RG 8 coaxial line. A student buys an RG 8 low-loss coaxial cable for a VHF antenna project. He looks up the specifications of the RG 8 coax in a product catalog and finds out that its characteristic impedance is Z0 = 50 Ω, its velocity factor is vp/c = 0.66, and its line capacitance is C = 26.4 pF-ft−1. He then cuts a portion of this coax and measures the diameter of the inner conductor and the outer diameter of the dielectric to be approximately 2 mm and 7.5 mm, respectively. Using these values, find or verify the values of the unit length line parameters L, C, R, and G and the characteristic impedance Z0 of this cable at 100 MHz. Note that the dielectric inside RG 8 coax is polyethylene and that the leakage conductance per unit length of a polyethylene-filled coaxial line at 100 MHz is approximately given by G ≃ 1.58 × 10−5/ ln(b/a) S-m−1. Get solution
45. Two-wire line. Calculate the per-unit-length line parameters L, C, R, and G and the characteristic impedance Z0 of an air-insulated two-wire line made of copper wires with wire separation of 2.1 cm and wire diameter of 1.2 mm at a frequency of 200 MHz. Get solution
